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CPLD
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CPLD

 

The development of programmable logic devices has dramatically changed the methodology of prototyping of digital hardware. In traditional designs using large number of ICs, students spend most of the time in bread boarding. This puts limitation on the complexity of the design. However the modern Programmable Logic Devices (PLDs) have made the implementation of medium capacity logic circuit quicker, flexible and cost effective. In recent years the PLDs have enormously increased in capacity and complexity. Due to increasing popularity of such devices, there is a great demand of engineers with the knowledge of PLDs in industry. So many universities have introduced a course on programmable logic devices at least at PG level. However with rapid development in this area, it has become mandatory to teach these concepts of reconfigurable hardware at the undergraduate level. Though some universities are already on the path to improve the teaching facilities, a first course in digital logic design has been a challenge mainly due to scaling up of the laboratory facilities at UG level. Hence, apparently in most of the institutes students are left with simulation using CAD/development tools without having any hands on experience with such devices.

The Wadhwani Electronics Lab research team provides a low cost solution to teach concepts of digital design using a CPLD with minimal requirements on the student's part. The main objectives of the proposed CPLD Lab at WEL are:

  • To help the students to better understand the concepts of logic design
  • To complement one semester theory course in digital design
  • To give the students hands on experience with the process of reconfigurable logic design, implementation and verification of logic systems using modern designing tools for digital logic design using an affordable CPLD board designed at WEL Lab
  • To make the student confident to use state of art technology

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